Cisco Silicon One Q201 and Q201L Processors Data Sheet
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The silicon industry has always been plagued with the trichotomy of switching silicon, routing line card silicon, and routing fabric silicon. Using these three basic building blocks, silicon and system vendors created unique architectures tuned for individual markets and industries. Consequentially, forcing customers to consume and manage these disjointed and dissimilar products caused an explosion in complexity, CapEx, and OpEx for the industry.
The Cisco Silicon One™ architecture ushers in a new era of networking, enabling one silicon architecture to address a broad market space, while simultaneously providing best-of-breed devices.
At 6.4 Tbps, the Cisco Silicon One Q201L builds on the ground-breaking technology of the Cisco Silicon One Q200L but brings the efficiency and flexibility of Cisco Silicon One and 7 nm down to the 64x100GE spine and leaf switches. The Q201 provides similar advantages for the WAN and peering routers, enabling a 64x100GE deep-buffered and high-scale router.
The Cisco Silicon One Q201 processor is a 6.4-Tbps, full-duplex, standalone routing processor with deep buffers, while the Q201L is a 6.4-Tbps, full-duplex, standalone switching processor.
Cisco Silicon One Q201 can be used to build fixed form factor routers ideally targeted for core, peering, and DCI applications. The Cisco Silicon One Q201L can be used to build fixed form factor switches ideally targeted for data center spine and leaf applications.
Table 1. Architectural Characteristics and Benefits
| Feature |
Benefit |
| Unified architecture across multiple markets |
Greatly simplifies customer network infrastructure deployments |
| Unified SDK across market segments and applications |
Provides a consistent point of integration for all applications across the entire network infrastructure |
| High-performance routing and switching silicon |
Achieve line rate at small packet sizes |
| Power-efficient routing and switching silicon |
The power efficiency of 7 nm and the Cisco Silicon One architecture |
| Large and fully unified packet buffer |
Fully shared on-die buffer with optional large, external packet buffer |
| Switching efficiency with routing features and scale |
Addresses the requirements of service provider and web-scale providers’ routing and switching applications |
| Run-to-completion network processor |
Provides feature flexibility without compromising performance or power efficiency |
| P4 programmable |
Leverages an open-source programming language to enable customers to define their own features |
Flexibility, Performance, and Scale for Next-Generation Service Provider and Web-Scale Networks
Features
● 256 28G SerDes; each can be configured independently to operate in 10G/25G using NRZ modulation
● Flexible port configuration supporting 10/25/40/50/100 Gbps
● Large, fully shared, on-die packet buffer
● Large, in-package packet buffer (Q201 only)
● 1588v2 and SyncE support with nanosecond-level accuracy
● On-chip, high-performance, P4-programmable host NPU for high-bandwidth offline packet processing (for example, OAM processing, MAC learning)
● Multiple embedded processors for CPU offloading
Traffic Management
● Large pool of configurable queues, supporting DiffServ and hierarchical QoS
● Support for system-level, end-to-end QoS and scheduling for both unicast and multicast traffic
● Seamless extension of on-die buffer to external packet buffer
● Support for ingress and egress traffic mirroring
● Support for link-level (IEEE802.3x), PFC priority-level (802.1Qbb) flow control and ECN marking
● Support of port extenders
NPU
● Run-to-completion, distributed, P4-programmable NPU architecture
● Line rate at very small packets with complex packet processing
● Large and shared NPU fungible tables
● Support of demanding packet processing features without impacting data rate
● Support of simple packet processing features while optimizing power and latency
Load Balancing
● Flow load balancing using ECMP or LAG
● Dynamic flowlet load balancing with ability to detect and handle elephant flows
Instrumentation and Telemetry
● Programmable meters used for traffic policing and coloring
● Programmable counters used for flow statistics and OAM loss measurements
● Programmable counters used for port utilization, microburst detection, delay measurements, flow tracking, elephant flow detection, and congestion tracking
● Traffic mirroring: (ER)SPAN on drop
● Support for sFlow and NetFlow
SDK
● APIs provided in both C++ and Python
● Configurability via high-level networking objects
● Distribution-independent Linux packaging
● Robust simulation environment enables rapid feature development
● CPU packet I/O through native Linux network interfaces
P4 Programmability
● Application development is handled by a P4-based IDE programming environment
● At compilation, the P4 application generates low-level register/memory access APIs and higher-level SDK Application APIs
● Provides application support for a wide range of data center, service provider, and enterprise protocols
● Modifications to the provided application can be easily accomplished using the provided P4 development environment
● Ability to develop the SDK and applications running over the SDK over a simulated Cisco Silicon One device
Cisco P4 Application
Due to Silicon One’s extensible P4 programming toolkit, we are always adding features to address new markets and new customer requirements; however, a sample of the features that are currently available with the P4 code is provided below:
|
◦ OSPF ◦ IS-IS ◦ BGP
● MPLS Forwarding
◦ LDP, LDPoTE ◦ RSVP-TE ◦ SR-MPLS ◦ SR-TE ◦ L3VPN, 6PE, 6VPE ◦ BGP LU ◦ VPWS/EoMPLS ◦ VPLS
● Ethernet Switching
◦ 802.1d, 802.1p, 802.1q, 802.1ad
● IP Tunneling
◦ IPinIP ◦ GRE ◦ VXLAN
● Integrated Routing and Bridging (IRB)
● HSRP/VRRP
● Policy-Based Routing
● Security and QoS ACLs
|
● ECMP and LAG (802.3ad)
● Multicast
◦ PIM-SM/SSM ◦ IGMP ◦ MLDP ◦ MVPN
● NAT/PAT
● Protection (Link/Node/Path and TI-LFA)
● QoS Classification and Marking
● Congestion Management
● Telemetry
◦ NetFlow, sFlow ◦ (ER)SPAN ◦ Packet Mirroring with Appended Metadata ◦ Lawful Intercept
● DDoS Mitigation
◦ Control-Plane Policing ◦ BGP Flowspec
● Timing and Frequency Synchronization
◦ SyncE ◦ 1588 |
Information about Cisco’s environmental, social, and governance (ESG) initiatives and performance is provided in Cisco’s CSR and sustainability reporting.
Table 2. Cisco environmental sustainability information
| Sustainability Topic |
Reference |
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| General |
Information on product-material-content laws and regulations |
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| Information on electronic waste laws and regulations, including our products, batteries, and packaging |
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| Information on product takeback and resuse program |
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| Sustainability inquiries |
Contact: csr_inquiries@cisco.com |
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| Material |
Product packaging weight and materials |
Contact: environment@cisco.com |
Learn more about the Cisco Silicon One